Core matrix coded decimal parallel adder utilizing propagated carries



Jan. 19, 1965 CORE MATRIX CODED DECIMAL PARALLEL ADDER H. W. COCHRANE-UTILIZING PROPAGATED CARRIE-S Original Filed June 28. 1960 17Sheets-Sheet 1 FIG 1 5% STORAGE REG|STER SELECT W 40 CURRENT 5s ems eeruucnon AND CURRENT Mu om STORAGE WES SELECT swncn 42 68 w FUNCTIONINPUT INPUT BUFFER SELECT L DEVICE CURRENT ems flifi ifl j/j Q/ FUNCTIONAL LQ EHJ SELECT ACCUMULATOR CURRENT REGISTER Z2 ADDERMTRCES 46 GATESINHIBIT SWITCHES 1' FUNCTION SELECT CURRENT I PRIMARY 16 L "5339 I...

STORAGE I OUTPUT 74/ DEVICE 184 92 1as CONTROL PULSE GENERATOR 1 65 Wmeo W 5% 41 AccunuLAToR PROGRAM STORAGE CONTROL ADDRESS REGISTER REGISTERnsm REGISTER 4| 1 l 61/ \NVENTOR HARRY W. COCHRANE Jan. 19, 1965 H. w.COCHRANE 3,1

CORE MATRIX CODED DECIMAL PARALLEL ADDER UTILIZING PROPAGATED CARRIESOriginal Filed June 28, 1960 17 Sheets-Sheet 5 FIG 3 ALPHA-NUMERIC CODECHARACTER CODE 1 EQUIVALENT CARD CHARACTER DICIT CHARACTER DICIT CODEREPRESENTATION ZONE CHARACTER ZONE CHARACTER ZONE v DICIT NUMERICCHARACTER ALPHABETIC Jan 19, 1965 H w COCH I RANE 3 1666 GORE MATRIXCODED DECIMAL PARALLEL ADDER UTILIZING PROPAGATED CARRIES Original FiledJune 28. 1960 17 Sheets-Sheet 8 WRITE 5 sao RESET 414 GATE X/ADDERIIIITRIcIZs' GATE n n ToE' 4I o 4I 2 I 590 592 406\ -I-- 584 8" E l IPARTIAL SUM 52% $0: E I AND 2. INITIALCARRY 2 I /sa2 I 22% GENERATOR 5 II PM u.I I O0 00 598 0.0 H H I 596 l I 588 A2 1 x50 7 TAccuMuLAToR CARRYI-STORAGE 1 I REGISTER REGISTER l IREGISTER I l ..I]] I 4l l I F|G.'5A

m DIGIT SENSE LINES m CARRY SENSE LINES (f: N09 INHIBIT LINES 2: CARRYWRITE LINES DIGIT INHIBIT LINES o I 2 3 4 5 e T a 9 0 o I 2 3 4 s 6 7 sI I 2 3 4 s a I a 9 I0 2 2 3 4 5 e 7 8 9 10 II FIG. 8

3 3 4 5 s I 8 9 III II I2 4 4 s e I a 9 I0 II I2 I3 5 5 e 7 a 9 I0 II I2I3 I4 6 e I a 9 I0 II I2 I3 15 I I a 9 10 II I2 I3 I4 15 16 s a 9 III III2 I3 I4 I5 Is 17 9 9 I0 II I2 I3 I4 15 16 17 18 LINES 582 FROMACCUIIULATOR REGISTER Jan. 19, 1965 Original Filed June 28; 196

H. W. COCHRANE CORE MATRIX CODED DECIMAL PARALLEL ADDER UTILIZINGPROPAGATED CARRIE-S 1'7 Sheets-Sheet 9 LINES 5110 1 FROM F r J z 1 Y1111111111 2 1 Y men o 1 o 1 2 3 11 /READ/ mt WRITE PARTIAL z 2 x r 4101mm mIIl AL 110 9 DIZGJT SUM CARRY -AND 085 406 t READ/WRITE READ/WRITECARRY Z 2 X INHIBIT DIGITI AMP OVERFLOW INDICATION PROPAGATED W4 SENSEDIGIT I9 LINES 586 T0 Jan. 19, 1965 CORE MATRIX CODED DEICIMAL PARALLELADDER H. W. COCHRANE 17 Sheets-Sheet 10 STORAGE REGISTER Z1Y INHIBIT Z1YIIIIIIIIII H6. 68

men 2 DIGIT I i "=READ/WRH'E 406b 406b sIIII FUNCTIONAL N09 SELECT TOTALg; IIIIIIIIL -AN'D CURRENT SUN 5. CARRY I I GATE GENERATOR READlwRlTE5'6 70l1 READ/WRITE I PARTIAL FUgECLTgAL I "IIIII mm s- INITIAL CARRY QI GENERATOR 4m 4060' 422b 4 2 [4626 2 a 424a I 4Iab 106a 41a CARRY SENSEr CARRY SENSE MD I412) 456m, AMP -AND mp I 42% any 419a, cIIIIIIII MDCARRY TRIGGER TRIGGER 0R l L41% 4 2 1300 130b L i T0 DIGIT 3 ERATOR 436043611 SENSE DIGIT 2 SENSE II'IcII I T G N J ACCUMULATOR REGISTER PARTIALSUM AND INITIAL CARRY GENERATOR REGISTER INPUTS I Jan. 19, 1965 H. w.COCHRANE CORE MATRIX CODED DECIMAL PARALLEL ADDER UTILIZING PROPAGATEDCARRIES Original Filed June 28, 1960 17 Sheets-Sheet 11 Y mman SENSECARRY SENSE X INHIBIT FROM STORAGE Y INHIBIT FIG. 7

CARRY SENSE Jan. 19, 1965 H. w. COCHRANE 3,166,669

CORE MATRIX CODED DECIMAL PARALLEL ADDER CARRIES UTILIZING PROPAGATEDOriginal Filed June 28. 1960 l7 Sheets-Sheet 12 Jan. 19, 1965 H w.COCHRANE 3,166,669

CORE MATRIX JODED DECIMAL PARALLEL ADDER UTILIZING PROFAGATED CARRIESOriginal Filed June 28. 1960 a 17 Sheets-Sheet 13 FIG. 9B

424 432 WRITE RESET Jan. 19, 1965 H. w. COCHRANE 3,166,669

CORE MATRIX CODED DECIM PARAL. E ADDER UTILIZING PROPAGAT CARR 17Sheets-Sheet 14 Original Filed June 28.

FIG.1O

mwwmw Jan. 19, 1965 H. w. COCHRANE 3,166,669

CORE MATRIX CODED DECIMAL PARALLEL -ADDER UTILIZING PROPAGATED CARRIESOriginal Filed June 28. 1960 ,17 Sheets-Sheet 16 FIG. "8

READ/ WRITE 434 4 CARRY -w Z CARRY-I 1 CARRY-I SA SA Jan. 19, 1965 H. w.COCHRANE 3,166,669

- CORE MATRIX CODED DECIMAL PARALLEL ADDER UTILIZING PROPAGATED CARRIESOriginal Filed June 28. 1960 17 Sheets-Sheet 17 ONE DIGIT POSITION OFTOTAL SUM GENERATOR ACCUMULATOR REGISTER Z 2 LINES FIG. 12

United States Patent O I s 166 see Conn MATRlX connnnncnrai. PARALLELADDER UTiLlZlNG rnorAeArnn mamas Harry W. Cochrane, Poughkeepsie, N.Y.,assignor to 9 Claims. 61. 225-475 This application is a division ofcopending application Serial No. 39,315, filed June 28, 1960.

This invention relates to information handling and data processingmachines or devices and more particularly to a core matrix adder.

General objects of the invention are to increase. computer performanceper unit cost, to increase speed of operation, reduce unit costs, andimprove reliability of operation particularly incomputers of the typethat employ stored programs and which may be controlled by standardprogramming methods.

A specific object is to .provide an improved parallel adder.

Another object is to provide core matrices. v V A further object of theinvention is to provide. a number of core matrices making up an adderincluding a matrix which generates propagated carries in developing afinal sum.

A feature of the invention is an extended use of core matrices inarithmetic and logic operations as well as in memory units and inprogramming, including branch programming.

A specific feature is an improved adder and method of addition.

Another feature is a propagated carry generator A core matrix as usedherein is a group of magnetic cores which are interlinked by -aplurality of conductors, each of which conductors is coupled to one ormore of the cores in the group.

A core or magnetic core as used herein is composed of magnetic materialwhich exhibits a hysteresis effect. In one typical form, such a coremaybe employed as a bistable device. Thus if driven magnetically in onedirection, as by means of one or more conductors coupled to the core, itwill assume one magnetized state and will remain substantiallyindefinitely in that state until, by the application of sufficientmagnetizing force in the opposite sense, as by means of the same orother conductors, it may be driven magnetically in the oppositedirection. The transition from one state tothe other will produce, inany conductor coupled to the core, a useful output signal of onepolarity or the other depending upon the direction of the transition.The two a parallel adder utilizing 'stable states of such a core may beused to represent respective items of information; for example, onestate may be used to represent the binary digit one and the other statemay be used to represent the binary digit zero.

Although magnetic cores have been illustrated herein for use as storageelements in the system described herein, it will be understood thatother types of storage elements may be employedin'stead in the system. 5

The terms line, conductor, and winding will be used hereininterchangeably to mean a conductor such as may be coupled to one ormore cores.

The normal state of a core will generally be designated as the zerostate. A core may be set up, set on or switched whereupon it will thenassume or be flipped into the one state. To flip a core requires thepassage of at least a certain minimum amount of current through3,165,669 Patented Jan. 19, 1965 a wire coupled to the core and thiscurrent must be in the proper direction to reverse the magnetic flux inthe core.

Magnetic cores made of ferrite, of toroidal shape and as small as 0.030inch inside diameter and 0.050 inch outside diameter may be used. Suchcores permit the assembling of complicated matrices in very limitedspaces. Coupling sufiicient forthe purposes of the invention isobtainable by threading a wire once through the toroidal core. describedherein, many wires are required to be threaded through a single core,wires as small as No. 36 or smaller may be used with cores as small as0.050 inch inside diameter and 0.080 inch outside diameter. These coresare smaller than cores generally known as switching cores, require lesspower to operate, less magnetomotive force to effect a reversal ofstate, and in the system described herein, provide rapid operation.

In the known half-select method of selectively setting on one or morecores in a matrix while leaving other cores in whichever state each suchcore happens to be in, pulses each of half the amount required to set upa core may be passed simultaneously through two sep arate conductorscoupled to the core in like polarity and these pulses will combine theireffects to set up the core. Each such pulse is called a half-selectpulse.

A core which receives only one half-select pulse over I the totality ofconductors coupled thereto will not be set up, and, upon cessation ofthe current will return to its zero state. By the application ofhalf-select pulses to a group of cores, one core may be set' up to theexclusion of all other cores in the group. This occurs where twoconductors each carrying a half-select pulse are each coupled to aplurality of' cores and one or more of the cores is coupled to bothconductors.

A core is said to be inhibited if a conductor coupled to the core iscarrying a current, of suitable magnitude, opposed in direction to theselect current. An

uninhibited core is one to which no inhibiting current is applied. Anuninhibited core may be flipped by a conductor carrying a select currentor a current of greater amplitude than a select current.

In certain portions of the illustrative system described herein, insteadof using a half-select principle of operation, an arrangement isemployed for applying inhibit currents of large amplitude to cores whichare not to be selected, and for applying a write current, for flippinguninhibited cores, of correspondingly large amplitude, providing itsamplitude does not exceedthe amplitude of the inhibit current in thecores that are not to be flipped. The inhibit and write-in currents maybe several times larger than would be necessary to write into anuninhibited core. Accordingly, very reliable and rapid action may beobtained by over-driving the uninhibited core. At the same time,inhibited cores will not be flipped. It is assumed that all the coresinvolved are initially in the same state, usually the zero state. In thecase of saturable cores, the inhibiting magnetomotive force and thewrite-in magnetomotive force preferably exceed, as by several times, theminimum magnitude of magnetomotive force necessary to saturate anininhibited core.

This over-drive inhibit principle is used herein for selectively settingup cores in a matrix, being used in some instances instead of thehalf-select principle.

To read out the information in a core, a read-out pulse of current isimpressed upon a conductor coupled to the core. This current is madeoppositeto a select pulse in its effect upon the state of the core. Itwill be noted that the direction of the read-out current is the same asthe direction of an inhibit current, but the amplitude of the read-outcurrent will generally be less than the amplitude of the inhibitcurrent, the amplitude of the Where, as in some of the matrices" Jread-out current being about the same as the amplitude of a selectcurrent. That is, the read-out current or readout pulse is of a polarityand amplitude to return a set-on core to its normal or off state,usually the zero state, and to provide an output pulse from the core ifand only if said core has previously been switched to its other stablestate, as by either the half-select principle procedure or by theinhibit principle procedure combined with a write pulse. Each core in amatrix is coupled to one or more output windings known as sense lineswhich carry a pulse when the core is switched from the one state to theother. In general, there will be employed a plurality of sense lineseach of which is coupled to a plurality of cores, so that when any oneof the cores coupled to this sense line has a read-out pulse impressedupon a read-out line coupled to the core, an output pulse will appear inthe associated sense line, provided the core previously has beenswitched to the one or on state.

In the embodiment illustrated herein, there are provided a core matrixmemory unit and one or more operation performing or functional corematrix units, in particular, an arithmetic unit and one or more logicunits. There are also provided a plurality of registers including astorage register, an accumulator register and a control information oroperation code register. Each register has associated therewith an inputgate individual thereto. A plurality of sense lines pass through all thecore matrix units. Each sense line is coupled to one or more cores ineach matrix in such a way that when a matrix is subjected to a read-outoperation, output pulses are generated in those of the sense lines thatare coupled to one or more cores which have previously been set on by awrite-in operation. Since the sense lines as a group pass through aplurality of matrix units, the sense lines will be referred to as commonsense lines.

A first set of inhibit core drivers is provided, the general purpose ofwhich is to impress inhibit currents upon those cores in any givenmatrix which are to be prevented from being set on when a write-inoperation is performed. Inhibit lines from the set of drivers areconnected serially through the various core matrix units and are used ona time sharing basis, for which reason the set of drivers will generallybe referred to as common first inhibit drivers. A set of common firstinhibit drive lines are provided to convey information for setting up afirst pattern of inhibit currents or pulses from one of the registers tothe common first inhibit drivers and thence to transmit the requiredpattern of inhibit currents or pulses to one or more of the core matrixunits. In the illustrative embodiment, the common first inhibit drivelines run from the storage register to the common first inhibit driversand thence to the memory unit, the arithmetic unit and one or more logicunits. The arithmetic unit will be said to have first and second inputdimensions, meaning that an addend and an augend are presented to theunit over separate systems of drive lines. It will be assumed that theaddend is stored in the storage register. The common first inhibit drivelines then impress information about the addend upon a first dimensionof the arithmetic unit.

A second set of common drivers is provided which will be referred to asthe common second inhibit drivers. A set of common second inhibit drivelines is also provided to convey information for setting up a secondpattern of inhibit currents or pulses from another of the registers tothe common second inhibit drivers and thence to transmit the requiredpattern of inhibit currents or pulses to a second dimension of the samecore matrix unit to which the first pattern of inhibit currents orpulses is supplied. In the illustrative embodiment, the common secondinhibit drive lines run from the accumulator register to the commonsecond inhibit drivers and thence to a second dimension of thearithmetic unit, to impress information about the augend upon thearithmetic unit. They are also extended to one or more other logicunits.

Control lines originate in the output of a control pulse generator undercontrol of the control information register or operation code registerand connect to the respective gates, both input gates and output gates,to supply gate pulses to the gates selectively as required by thevarious operations to be performed.

To supply write pulses or read pulses as required, there is provided aset of matrix unit drivers, which are called common unit drivers and maybe time shared by various matrix units. A set of common unit drive linesis provided which may be connected to the respective matrix unit driverswhen desired. The common unit drive lines are divided into a pluralityof parallel branches which connect respectively to the various corematrix units. In each core matrix unit, the unit drive lines connect tothe respective matrix unit output gate so that when an output gate pulseis applied to a matrix unit output gate a circuit is completed for thecommon unit drivers through the selected matrix unit and its associatedoutput gate to supply a read pulse to the matrix unit. In general, eachmatrix unit is provided with two gates, a read gate which may beregarded as the output gate, and a write gate or input gate whereby acircuit is completed for the common unit drivers to supply a write pulseto the matrix unit.

The control pulse generator is provided with means for selectivelyenergizing the control lines to effect the transfer of either controlinformation or data information over the common sense lines to any oneor more of the registers under the joint control of the control linesand of the unit drive lines. In particular, in an addition operation,the selective means incorporated in the control pulses generator isoperative to effect the transfer of control or data information from thestorage register over the common first inhibit drives lines to the firstdimension of the core matrix arithmetic unit and also to effect thetransfer of control or data information from the accumulator registerover the common second inhibit drive lines to the second dimension ofthe core matrix arithmetic unit. With information thus having beensupplied to two dimensions of the arithmetic u-nit, the informationitems may be combined in the arithmetic unit and the result may be putonto the common sense lines for further disposition as desired.

In several of the figures, certain components are shown in block diagramform with letter identifications, for example, triggers T, trigger gatesTG, and-circuits A, or-circuits 0, core drivers CD, current gates CG,inverter I, emitter followers E, and sense amplifiers SA. illustrativeexamples of circuits for such components are shown in FIGS. 31 through39 of said copending application Serial No. 39,315.

Other objects, features and advantages will appear from the followingmore detailed description of illusrative embodiments of the invention,which will now be given in conjunction with the accompanying drawings.

In the drawings,

FIG. 1 is a general block diagram of an embodiment of the invention;

FIGS. 2A, 2B, 2C, arranged as shown in FIG. 2 comprise a combinationblock diagram and How sheet of an embodiment similar to that shown inFIG. 1;

FIG. 3 is a chart showing an alpha-numeric code suitable for use in asystem embodying the invention;

FIGS. 4A and 43 arranged side by side comprise a set of schematicdiagrams showing systems of time shared sense lines together with blockrepresentations of input gating arrangements for a plurality ofregisters which may be connected to receive signals from the sense lineson a time sharing basis;

FIG. 5 is a combination block diagram and iiow chart of an adder whichmay be a component of a system embodying the invention, FIG. 5A showingthe significance of various lines of flow shown in FIG. 5;

FIGS. 6A and 63 arranged side by side comprise a detailed schematicdiagram of an adder of the type shown more generally in FIG. 5;

FIG. 7 is a wiring diagram of a partial sum and initial carry generatorvwhich may form part of the adder shown in FIGS. 5 and 6; g

FIG. 8 is a table of addition useful in explaining the operation of thepartial sum and initial carry generator;

FIGS. 9A and 9B arranged side by side comprise a schematic diagram of apropagated carry generator which may form part of the adder shown inFIGS. 5 and 6;

FIG. 10 is a simplified schematic representation of the Wiring scheme ofthe propagated carry generator shown in the diagram of FIG. 9;

FIGS. 11A and 11B arranged one above the other comprise a schematicdiagram of a fragment of an adder of the type shown in-FIGS. 5 and 6;and

FIG. 12 is a wiring diagram of a total sum generator which may form partof the adder shown in FIGS. 5 and 6.

Time sharing and internal routing Referring to FIG. 1, an assemblage ofcore matrices is indicated in block form, comprising an instruction anddata storage or memory section lt an input buffer 42, a plurality'ofmiscellaneous functional matrices 44- and a group 46 offunctional'matrices specific to addition and "subtraction,includingcar'ry generation and carry propagation. Instructions and datamay be put into the instruction and data storage section 4% by way ofthe input buffer 42 by means of an input device 48. Information sointroduced preferably does not go directly into the storage section 49from the buffer but is first routed to a storage register 50 over asystem of time shared sense lines. These lines pass through the matrixunits 449, 42, 44, 46 to the storage register 50, and to a programaddress register 6%, an accumulator register 62 and an operationalcontrol register 63, in each of which information may be temporarilystored as by means of triggers. At a suitable time the triggers in thestorage register 50 selectively actuate a set of Z inhibit switchescomprised in block 52, thereby energizing a first set of inhibit drivelines which thread through the assemblage of matrices where they may bemade available for use in any matrix by means of in ut gatesindividualto the various matrices. Instructions or data may be written into orread out of any selected address in the instruction and data section 49under the control of an X select switch 54, a Y select switch 56 and aset of function select current gates 5%.

An instruction read out of the memory section 49 may be transferred overthe common sense lines to the program address register 6% and theoperation control register 63 where information contained in theinstruction may be stored temporarily and used in the register 69 tocontrol the movement of data or instructions into or out of memory andin the register 63 to control the performance of functional operationsupon either data or instructions through an operation word storage unit92 and a control pulse generator 188 actuated by a primary timer 134.Some of the main control paths are indicated by a cable 61 originatingin the register 66) and a cable 65 originating in the control pulsegenerator 133.

Information on data or instructions may be moved from memory or from anyfunctional matrix to the ac- 42 is controlled by function select currentgates com prised in a block 66. Functional operation of the matrices 44is controlled by a set of function select car- 6 rent gates 68-andfunctional operation of the adder is controlled by function selectcurrent gates 70.

Information may be read out of the computer from any matrix level by wayof an output buffer 72 into an output device 74 but preferably does notgo directly to the output buffer from the matrices, being routed overthe common sense lines to the storage register, from which it goes overinhibit lines to the output bufier.

By routing the bulk of all infermation transfer always through eitherthe storage register or the accumulator register, error checking may beconcentrated in two places, one associated with each said register,thereby facilitating the detection of errors.

In FIG. 2, the system components shown in FIG; 1 are supplemented byadditional components and developed in the form of a flow chart for thefiow of instructions and data over the various time shared sets ofinterconnecting lines, more particularly the sense lines, inhibit linesand control lines. The apparatus components in FIG. 2 will be describedin groups associated with the various sets of lines.

A first system of time shared lines comprises the output lines of thestorage register 56 and a set of Z inhibit lines controlled by thecontents of the storage register. Cables 8t) and 82 are shown emergingfrom the storage register, of which cable carries information regardingthe lower order digits and cable 82 regarding the higher order digits.As part of the same general system, inhibit cables 8.12, 83 emerge fromthe switch block 52.

The cable 84 passes through a set of true-cornplement switches in block84, to provide for either addition or subtraction, and thence to thestorage register Z inhibit switch and driver block 52. Thence cable 81passes through an input-output address register 552 to be describedbelow, a Z error detection block 86, the instruction and data storage4'3, a mask-shift functional matrix block 88, a multiplier-quotient (MQ)register 96, the adder 56, and thence to the output buffer 72.

The cable 82 passes directly to the storage register Z inhibit switchand driver block 52. Thence cable 83 passes through the Z errordetection block 86, and the maskshift functional matrix block 88 to theadder 46.

A second system of time shared lines comprises the output of theaccumulator register 62 and a set of Z inhibit lines controlled by thecontents of the accumulator register. Cables and 96 are shown emergingfrom the accumulator register and running to the Z inhibit switch anddriver block as, which cables relate to the lower order and higher orderdigits respectively. Cables hi and 97 emerge from the accumulatorregister Z inhibit switch and driver block 64 and pass through a Z errordetection block 98 to the adder 46 and thence to the mask-shift matrixblock 88.

A cable 99 is provided to transmit the data'address digits from theprogram address register 60 to the Z inhibit switch and driver block 64,for use when a program address is to be operated upon in the ladder.

A third set of inhibit lines comprising five 2;, lines in a cable 41runs from an input register switch and driver block Edit) to the inputbufier .42. The block 1% receives an input from the input device 48through an input translater 102. s

A set of time shared word sense lines for the lower order digits,represented by a cable 104 originates in the instruction and datastorage 40 and passes through the input buffer 42 the-mask-shift matrix88, the MQ register )9, the adder 46 and thence to a set of senseamplifiers 106. At the output of the sense amplifier block 1%, the cable104 branches. A branch goes to the program address register 60 through'aprogram address register gate block 1%. Another branch goes to a programindex address register 61 through a program index address register gate.block 1&9. Other branches go respectively to a mask-shift register 57through a mask-shift register gate block 107; to

an operation code register 63 through an operation code

9. IN A DIGITAL COMPUTER FOR ADDING A MULTITUDE ADDEND TO A MULTIDIGITAUGENED, IN COMBINATION, AN ADDER OF A TYPE THE DEVELOPS A PARTIAL SUMDIGIT FOR EACH DIGIT POSITION OF THE SUM WITHOUT REGARD TO CARRY ANDWHICH SEPARATELY INDICATES AN INITIAL CARRY IN EACH DIGIT POSITION INWHICH A CARRY ORIGINATES, A REGISTER FOR SAID PARTIAL SUM, A CARRYREGISTER FOR SAID INITIAL CARRIES, MEANS FOR APPLYING INFORMATIONDEFINING SAID ADDEND AND SAID INITIAL CARRIES AND TO TO DEVELOP SAIDPARTIAL SUM AND SAID INITIAL CARRIES AND TO PLACE THE RESULTANTINFORMATION IN SAID RESPECTIVE REGISTERS, MEANS CONTROLLED BY BOTH SAIDREGISTERS TO DEVELOP ALL RESULTANT PROPAGATED CARRIES AND TO REGISTERSAID PROPAGATED CARRIES IN SAID CARRY REGISTER TOGETHER WITH SAID INTIALCARRIES, AND MEANS CONTROLLED BY SAID CARRY REGISTER FOL-